1. Field of the Invention
The present invention provides a method for making an active pixel sensor, especially an active pixel sensor with a photodiode having an increased quantum efficiency (QE).
2. Description of the Prior Art
An active pixel sensor is a semiconductor device comprising an N-type channel metal-oxide semiconductor (NMOS) transistor, or a complementary metal-oxide semiconductor (CMOS) transistor, and a photodiode. It is commonly used as an image sensor for a photoelectric product, such as a camcorder or a scanner.
In current semiconductor processes, the metal-oxide semiconductor device in the active pixel sensor, the active pixel sensor region including photodiode, and the periphery circuit which includes other devices, are all made on a single chip. The periphery circuit not only comprises a plurality of CMOS transistors composed of an N-type channel metal-oxide semiconductor (NMOS) device and a P-type channel metal-oxide semiconductor (PMOS) device, but also comprises devices like resistors and capacitors. In the image sensor fabrication process, the CMOS transistors in the periphery circuit, the N-type: channel metal-oxide semiconductor device, and the photodiode in the active pixel sensor region all need to be integrated together. Therefore, an N-well ion implantation process in a typical CMOS transistor process is used as the first ion implantation process in the fabrication process of an image sensor chip.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art active pixel sensor 10. A photosensing area 20 for the prior art active pixel sensor 10 is positioned on a semiconductor wafer 11. The semiconductor wafer 11 comprises a silicon substrate 12 and P-well 14 positioned on the silicon substrate 12. The active pixel sensor 10 comprises an N-type channel metal-oxide semiconductor (NMOS) transistor 16 positioned on the surface of the p-well 14, and the photosensing area 20 positioned on the surface of the P-well 14 for electrically connecting to a drain of the NMOS transistor 16. The semiconductor wafer 11 further comprises a plurality of field oxide layers 18 on the surface of the silicon substrate 12. The field oxide layers 18 surround the photosensing area 20 and serve as an insulating material to prevent short-circuiting between the photosensing area 20 and other devices.
Please refer to FIG. 2. FIG. 2 is a schematic diagram of the prior art active pixel sensor 10 with a common area shared by a drain 17 and a doping area 22. In some embodiments, the source or drain of the NMOS 16 shares a common area with the doping area 22 in the photosensing area 20 in order to shrink the area of the active pixel sensor 10. The drain 17 is a high concentration doping area (N+), and the doping area 22 is a low concentration doping area (Nxe2x88x92).
As described above, the method for forming the prior art active pixel sensor 10 is to perform an N-well ion implantation process to the image sensor chip first. The N-well ion implantation process implants phosphorous ions with a dosage of approximately 1013/cm2 into the chip by utilizing an energy ranging from 100xcx9c200 eV to form an N-well. Then, a P-well, 14 ion implantation process is performed to the active pixel sensor region in the image sensor chip to form a P-well 14, The P-well 14 ion implantation process is a high energy boron ion implantation process with a dosage slightly higher than 1013/cm2. Since the N-well ion implantation process, which is a blanket implant process, is performed before the P-well ion implantation process to neutralize the N-well ion implantation process to form a P-well 14, the P-well ion implantation process is also called a compensation ion implantation process.
However, the two high-energy ion implantation processes usually cause damage of the single crystal structure on the surface of the P-well 14, which has drawbacks, such as increasing leakage current and inferior product reliability. Please refer to FIG. 3. FIG. 3 is a schematic diagram of an N-well and P-well ion implantation for the prior art image sensor chip 24. The relative sites for these two ion implantation processes for the chip are shown in FIG. 3A. The N-well ion implantation process is performed to the whole image sensor chip 24. That is, the diagonal line region in FIG. 3A, which includes the whole active pixel sensor area 26. An area covered by an N-well mask is the area for forming the PMOS devices in the periphery circuit region. As shown in FIG. 3B, the P-well ion implantation process is performed to the whole image sensor chip 24 outside the N-well mask 28, that is, the diagonal line region in FIG. 3B (the P-well ion implantation region), which also includes the entire active pixel sensor area 26.
The performance of a photodiode in terms of photosensitivity is characterized by leakage current. The light-induced current (light current) in the photosensing area of a photodiode in the presence of light represents a signal, while the current (dark current) in the photosensing area of a photodiode not in the presence of light represents noise. The photodiode utilizes signal-to-noise ratios to process signal data. The method to improve the quality of a photodiode is, currently, to increase the intensity of the signal represented by the leakage current in the photosensing area in the presence of light hence increase the contrast of signal by an increased signal-to-noise ratio, in order to enhance the sensitivity of the photosensing area of the photodiode, which further improves the quality of the photodiode.
Please refer back to FIG. 1. With arsenic ions in the photosensing area 20, a depletion region 24 is formed along the PN junction between the doped region 22 and the adjacent P-well 14. The method performs an ion implantation process, utilizing a high dosage of arsenic ions as the major dopant. The ion implantation process forms an N-type ion doping area 22 on the surface of the P-well 14, so the leakage current passing through the depletion region 24 with and without light represents signal and noise, respectively. The dotted lane region marked with slanting lines in FIG. 1 illustrates the depletion region 24. Since the N-type doping area 22 in the photosensing area 20 of the photodiode 10 utilizes high dosage arsenic ions as the major dopant, the doping area 22 formed completely by heavy doping processes will cause the depletion area 24 to have a narrower width when joined with the P-well 14 to form a PN junction. This decreases the area for the actual active region in the photosensing area 20, and decreases the light current passing through the depletion region 24 when the photosensing area 20 of the photodiode 10 is in the presence of light. Furthermore, the border between the edge of the dosing area 22 underneath the field oxide layer 18 and the P-well 14 tends to have larger leakage current for the PN junction when in the dark. Noise is therefore increased, and the signal to noise ratio is worsened, decreasing the signal sensitivity of the photosensing area 20.
In order to avoid decreasing of the actual active region caused by heavy doping processes, a structure with a common area shared by the source or drain and doping area 22 is utilized to clearly improve over the structure depicted in FIG. 1. Please refer to FIG. 2. The drain 17, with a high doping concentration, is not joined with the P-well 14. Only the doping area 22, with a lower doping concentration, is directly joined with the P-well 14.
However, the wafer structure destruction problem incurred by two high energy ion implantation processes cannot be avoided in the structure of FIG. 2. Please refer to FIG. 4. FIG. 4 is a schematic diagram of a prior art partial P-well active pixel sensor 30. The photosensing area 40 of the prior art active pixel sensor 30 is positioned on a semiconductor wafer 31. The semiconductor wafer 31 comprises a silicon substrate 32, and two P-wells 33 and 34 positioned in the silicon substrate 32. The semiconductor wafer 31 further comprises two field oxide layers 35 and 36 on the surface of the silicon substrate 32. The active pixel sensor 30 comprises an NMOS 38 between the two field oxide layers 35, 36, and a photosensing area 40 formed on the surface of the silicon substrate 32 sharing a common region with a drain 39 of the NMOS 38. The two field oxide layers 35, 36 positioned on the surface of the silicon substrate 32 surround the NMOS 38 and serve as an insulating material to prevent short-circuiting between the photosensing area 40 and other devices. The drain 39 of the NMOS 38 shares a common area with the doping area 42 to shrink the areas of the active pixel sensor 30. The drain 39 is a high concentration doping area (N+), and the doping area 42 is a low concentration doping area (Nxe2x88x92).
Please refer to FIG. 5. FIG. 5 is a schematic diagram of the N-well and the partial P-well ion implantation processes for the prior art image sensor chip 44. The N-well ion implantation process is performed to the active pixel sensor region 46 outside the photosensing area 40. Although there are some device regions in the periphery circuit area, such as the region for forming the NMOS, that are covered by a mask, they are not indicated in FIG. 5A. Then, as shown in FIG. 5B, the P-well ion implantation process is performed to the active pixel sensor region 46 outside the photosensing area 40. When performing the N-well and P-well ion implantation process, the photosensing area 40 is coveted by a mask.
In the structure disclosed in FIG. 4, the area occupied by the P-well is smaller, so the areas underneath the photosensing area 40 are all P-type silicon substrate 32. Therefore, destruction incurred from two high-energy ion implantation processes is avoided to resolve the drawbacks encountered in FIG. 1 and FIG. 2. In other aspects, however, new problems occurs. As shown in FIG. 4, P-well 33, 34 encroachment phenomenon may easily occur at the border between the P-well 33 and the drain 39, and at the border between the P-well 34 and the drain 39, due to a subsequent high temperature drive-in process. Once this phenomenon occurs, the actual area for photodiode shrinks. This will not only result in shrinkage of the active area, but also results in non-uniformity of the sensor area of the photosensing area 40 of different photodiodes 30, and thus leads to mismatching between different photodiodes. These are the main factors that degrade image quality.
It is therefore very important to develop an active pixel sensor with a new structure to avoid the above-mentioned wafer structure destruction problems that occur due to two high-energy ion implantation processes, and to avoid photodiode encroaching problems by the P-well. It is also desirable to form a depletion region with an adequate width and less structural defects to reduce noise and improve the absorption of red light.
It is therefore a primary objective of the present invention to provide a structure and method for making an active pixel sensor to improve the uniformity of the sensor area of the photosensing area in the photodiode, and the sensitivity of the photodiode, to resolve the above-mentioned problems.
In the preferred embodiment of the present invention, the method forms a first active pixel sensor block mask (APSB mask) to cover the active pixel sensor region first, then forms at least one N-well on the surface of the semiconductor wafer not covered by the first APSB mask. Thereafter, the first APSB mask is removed, and a second APSB mask and at least one N-well mask are formed on the surface of the semiconductor wafer to cover the active pixel sensor region and the region outside a P-well in the periphery circuit region, respectively. At least one P-well is then formed on the surface of the semiconductor wafer not covered by the second APSB mask and the N-well mask. Finally, the second APSB mask and the N well mask are removed, and at least one photodiode and at least one complementary metal-oxide semiconductor (CMOS) transistor are formed on the surface of the active pixel sensor region.
It is advantageous that the present invention first utilizes an active pixel sensor block mask to define the N-well of the PMOS transistor in the periphery circuit area, covers other portions of the wafer, and then perform the N-well ion implantation process. When making the active pixel sensor device afterwards, the P-well implantation is not performed, so the active pixel sensor device is formed on the P-type substrate. The photosensing area of the present invention photodiode is thus not surrounded by any P-well. Defects in wafer structure are reduced, the leakage current is lowered, and noise is reduced. Also, non-uniformity of sensor areas of the photosensing area of different photodiodes shows clear improvement, further improving the image quality. Under 550 nm incident light, the quantum efficiency of the present invention photodiode is raised to more than 60%.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.